A flash memory is one of the semiconductors which have an electrically rewritable nonvolatile memory area. The structure of a typical memory cell of the flash memory is shown in FIG. 4. This memory cell has a structure of 1 cell/1-bit, and is composed of a control gate 51, a floating gate 52, a source 53, and a drain 54. A transistor of such a structure is called a field effect transistor of floating-gate type.
FIG. 5 shows a part of a structure of a memory cell array including the above-mentioned memory cells. As shown in FIG. 5, the memory cell array is arranged so as to include m pieces of memory cells provided in a lengthwise direction and n pieces of memory cells provided in a crosswise direction in a matrix manner. The memory cell array further includes (i) m word lines WL1 through WLm that are connected commonly to the control gates 51 of the respective memory cells provided in the crosswise direction, and (ii) n bit lines BL1 through BLn that are connected commonly to the drains 54 of the respective memory cells provided in the lengthwise direction. The memory cell array further includes a source line SL that is connected commonly to the sources 53 of all the memory cells in a predetermined block.
Here, an operation in the memory cell array of the above structure is described briefly. The writing operation to the memory cell is performed as follows. First, a high voltage (for example, 12V) is supplied to the control gates 51 via the word line WL selected. Similarly, a high voltage (for example, 7V) is supplied to the drains 54 via the bit line BL selected. A low voltage (for example, 0V) is supplied to the sources 53. Under the circumstances, hot electrons generated near each of the drain junctions are injected into each of the floating gates 52. Thereby, the writing operation to the memory cell is completed.
On the other hand, an erasure operation to the memory cell is performed as follows. First, a low voltage (for example, 0V) is supplied to the control gates 51, a low voltage (for example, 0V) is supplied to the drain 54, and a high voltage (for example, 12V) is supplied to the sources 53. This causes, in the memory cell, a high electric field to be generated between the floating gate 52 and the source 53, and the electrons in the floating-gate is pulled toward the source 53 because of a tunneling effect. Thereby, the erasure operation to the memory cell is completed.
A read-out operation with respect to the memory cell is performed as follows. First, a high voltage (for example, 5V) is supplied to the control gates 51. Similarly, a low voltage (for example, 1V) is supplied to the drains 54, and a low voltage (for example, 0V) is supplied to the sources 53. And, the amplitude of the current flowing through the memory cell is amplified by an internal sense amplifier. “1” or “0” of data is judged in accordance with the current amplified.
Note that, during the writing, the voltage supplied to drains 54 is set lower than the voltage supplied to the control gates 51. This is because it is intended to avoid a parasitic weak writing (soft program) to the memory cell as much as possible. This is based on the fact that the plural memory cells are connected to a single word line and a single bit line, as mentioned above.
Thus, in order to perform the writing operation and the erasure operation (hereinafter referred to as “rewriting operation”) of the flash memory with high reliability, very complicated controls are needed. In view of the circumstances, in order to make the apparent usability better, many of recent semiconductor devices which carry the flash memory include a control circuit referred to as a state machine, and they can rewrite automatically.
In addition to the above memory cell array, the flash memory includes a control circuit, a booster circuit, a writing/erasure voltage generating circuit, a row decoder, a column decoder, and other circuits. The booster circuit operates during the writing of data, and generates a predetermined high voltage. The high voltage generated by this booster circuit is converted, by the writing/erasure voltage generating circuit, into a voltage needed during the writing/erasure operation. The voltage thus converted is supplied to the memory cell array, via the row decoder. Such a rewriting operation and a read-out operation are respectively performed under the control of the control circuit.
As described above, in a flash memory which is operated by a single power supply, the high voltage needed is generally generated by a built-in booster circuit. The booster circuit includes an oscillating circuit, a pump cell circuit, a reference voltage generating circuit, a comparator, a diode chain, and other circuits.
The comparator compares a reference voltage (a fixed voltage) outputted by the reference voltage generating circuit with a voltage that is obtained by stepping down an output voltage of the booster circuit via the diode chain. In accordance with a difference between the reference voltage and the voltage stepped down, the comparator outputs a bias signal for adjusting an oscillation frequency of the oscillating circuit. The oscillating circuit outputs an oscillating signal in response to the bias signal. The pump cell circuit boosts and outputs an inputted voltage in accordance with the oscillation signal.
An example of the conventional oscillating circuit is shown in FIG. 9. An oscillating circuit mainly includes a ring oscillator in which inverters NOT1 through NOT9 of odd number-stage (nine-stage in FIG. 9) are connected to each other in series. When it is assumed that a rising time of the inverter is indicated by Tr, a falling time of the inverter is indicated by Tf, and the number of stages of the inverters is indicated by 2n+1, the cycle of the oscillating circuit can be indicated by (2n+1)(Tr+Tf). When a wiring between two neighboring inverters is shortened, it is possible to reduce the influence of the nonuniformity of the oscillation cycle caused by the wiring load. This is because the delay time caused by the wiring load is shorter than the rising time or the falling time of the inverter.. Capacitors C1 through C9 shown in FIG. 9 are provided for an adjusting oscillating frequency so that the oscillating frequency does not become too large. That is, the capacitors C1 through C9 respectively function as delay circuits corresponding to the time required for charging or discharging the respective electric capacitance.
The above-mentioned capacitor may be realized by the electric capacitance made by two-layer polysilicons (hereinafter sometimes referred to as “poly” for short). The capacitor of such a structure is obtained by laminating a polysilicon or a metal on a gate poly after the gate poly is oxidized. The capacitor operates with high accuracy, and its characteristics change very little even if ambient temperature or the voltage changes. When the electric capacitance of the respective capacitors C1 through C9 shown in FIG. 9 is set to be larger enough than the parasitic capacity of the wiring (for example, 0.15 pF), most influences of parasitic capacity can be disregarded.
When an oscillating circuit does not operate, a start-up signal EN becomes a Low level and a BIAS signal becomes a High level. At this time, transistors P1–P9 and N–N9, which are connected to a power supply line of the inverters NOT1 through NOT9 and a GND line, respectively, will be turned off. This causes each input or output of the inverters becomes uncertain. However, since transistors N11, N12, N14 (not shown), N16 (not shown), N18 (not shown), P13, P15 (not shown), P17 (not shown), and P19 are turned on, the electric potential of the node to which each transistor is connected is determined.
An oscillating signal OSC outputted from the oscillating circuit is supplied to the pump cell circuit via an inverter NOT20. FIG. 9 deals with a case where the oscillating signal OSC is taken out from the output of the inverter NOT1. However, the oscillating signal OSC is not limited to this, provided that it is taken out from any one of the inverters (NOT1–NOT9 in FIG. 9) constituting the ring oscillator.
However, even if a capacitor whose characteristics change very little due to the changes in the ambient temperature or the voltage is used, the oscillating frequency of this ring oscillator will fall in proportion to decrease in the power supply voltage. This is because of the transistor characteristics of the inverters NOT1 through NOT9 constituting the ring oscillator. Moreover, the oscillating frequency will also be changed by the fluctuation in thresholds of the transistors generated during the manufacturing of the transistors, and by operating temperatures. For this reason, the booster circuit designed to operate with the minimum power supply voltage value will have the current supply capacity more than necessary when the maximum power supply voltage value is supplied to the booster circuit. As a result, the electric power supply will be wasted.
A conventional technology to solve the above-mentioned problem is disclosed in Japanese Patent Application Laid-Open (kokai) No. 325578/1993 (publication date: Dec. 10, 1993).” According to a method disclosed in this publication, it is possible to obtain the current supply capacity without depending on a power supply voltage, by making the oscillating frequency of an oscillating circuit higher in proportion to decrease in the power supply voltage.
The circuit structure disclosed in the publication includes (i) a nonvolatile memory main body, (ii) an oscillating circuit whose oscillation frequency becomes higher in proportion to decrease in the power supply voltage, and (iii) a booster circuit which generates a voltage required at the time of the writing/erasure of the above-mentioned memory means by boosting the power supply voltage in response to the driving of the above-mentioned oscillating circuit. The current supply capacity of the booster circuit tends to decline in proportion to decrease in the power supply voltage. However, the oscillating frequency of the oscillating circuit for driving the booster circuit becomes high in proportion to decrease in the power supply voltage. This negates the lowering of this current supply capacity. Thus, the booster circuit having the current supply capacity which does not depend on the power supply voltage is realized. On this account, it is possible to eliminate the waste of the electric power supply power due to the fluctuation of the power supply voltage during the writing/erasure.
Furthermore, according to a disclosure of Japanese Patent Application Laid-Open (kokai) No. 190798/1996 (publication date: Jul. 23, 1996)”, a nonvolatile semiconductor memory device includes a booster circuit having a boosting capability which is independent of manufacturing variations or the temperature change, thereby eliminating the waste of the electric power supply power during the writing/erasure. Such a nonvolatile semiconductor memory device has a similar circuitry to Japanese Patent Application Laid-Open (kokai) No. 325578/1993, except for an the oscillating circuit, in which a feature of memory device resides. A ring oscillator in the oscillating circuit is arranged such that a plurality of inverter circuits are mutually and circularly connected via respective MOS transistors for electric charge transfer. Gate electrodes of the MOS transistors are connected to output terminals of a voltage conversion circuit whose output voltage changes such that a transmission capability of the MOS transistor is improved in proportion to decrease in a power supply voltage.
However, these two conventional technologies mentioned above couldn't avoid the following problems. That is, there are two kinds of purposes for which the booster circuit has to supply the current quantity during a rewriting operation. One is for charging the load capacity, and the other is for supplying to DC paths. Note that the supplying of the current is no longer needed, once the load capacity is charged up to a high voltage. Moreover, since the rewriting operation is complicated as stated above, the DC path is not always generated. This causes the occurrence of a period in which a high potential is required only to be held. That is, the current quantity which the booster circuit has to supply will not be fixed. In this regard, in the two above-mentioned conventional technologies, the circuits are designed to hold the maximum current quantity required for the rewriting. This results in that the electric power supply power will be wasted when the current quantity less than the maximum current quantity is required.
As mentioned above, the conventional nonvolatile memory is designed so as to guarantee a proper operation even under the condition of the minimum current supply capacity, in view of (i) the fluctuation in the power supply voltage during the rewriting, (ii) the manufacturing variations, and (iii) the change, in the current supply capability of the booster circuit or the like, caused by the operation temperature. Therefore, as mentioned above, when the current supply capability less than the maximum one is necessary, there was a problem that the waste of electric power supply power happens.
Moreover, even if the arrangements like Japanese Patent Application Laid-Open (kokai) No. 325578/1993, or Japanese Patent Application Laid-Open (kokai) No. 190798/1996 is adopted in order to solve the problem of the change in the current supply capability, the waste of the electric power supply happens. This is because the circuit will be designed according to the maximum current supply quantity required for the booster circuit, if the current supply quantity changes during a series of operations such as the rewriting operation.
The present invention is made to solve the above-mentioned problems, and the object is to provide an oscillating circuit, a booster circuit, a nonvolatile memory device, and semiconductor device that have a feature that the oscillation frequency becomes low as the output voltage of a booster circuit becomes high, and that don't depend so much on any of the power supply voltage, temperature, or manufacturing variations.